The invention pertains to a dual path asynchronous delay circuit for introducing a delay into a system.
In telecommunications systems, bus interface systems and the like, it is sometimes desirable to delay certain signals to permit other portions of the system to respond to signal changes. For example, a bus expander circuit may delay signals on a primary bus to permit adequate turnaround time for signals on a secondary bus.
Analog delay cells have been developed for use in electronic circuitry to delay signals. Either the current or voltage available to a device can be varied, or the capacitive loading can be varied, to introduce a variable delay. A variable delay element can thus be built using inverters or other circuit devices.
A problem concerning the production of analog delay cells is that currents for p-channel and n-channel devices cannot be exactly matched. The inherent variations in processing, and differences in temperature and voltage, may result in devices that exhibit asymmetric drive. The asymmetric drive increases or decreases the pulse width of the signal as the signal pulse travels through a chain of delay cells, resulting in distortion or loss of the signal.
Another problem is that the delay of each cell in a chain of delay cells defines the minimum pulse width of a signal required to ensure that the signal will propagate through the entire chain. If a signal pulse width is too narrow, then as the signal propagates through consecutive stages of the delay chain at some point it will not attain a voltage sufficient to produce an output. Thus, it would be beneficial to develop a delay circuit that can propagate and delay a small pulse having a pulse width that is less than or equal to the delay provided by each delay cell.